1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to a liquid crystal display (LCD) device and a method for manufacturing the same that improve picture quality by decreasing the reflection of external light.
2. Discussion of the Related Art
With development of an information society, demands for various display devices have increased. As a result, efforts have been made to research and develop flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some types of flat display devices have already been applied to displays for various equipment. Among these flat display devices, liquid crystal display (LCD) devices have been most widely used because of its advantageous characteristics such as having a thin profile, light weight, and low power consumption. The LCD devices provide a substitute for a Cathode Ray Tube (CRT). In addition to mobile type LCD devices such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to receive and display broadcast signals. Despite the various technical developments in LCD technology having applications in different fields, research in enhancing the picture quality of the LCD device has, in some respects, lacked as compared to other features and advantages of the LCD device. In order to use LCD devices in various fields as a general display, the key to developing LCD devices depends on whether the LCD devices can provide a high quality picture, such as high resolution and high luminance with a large-sized screen, while still maintaining its light weight, thin profile, and low power consumption.
In general, the LCD device includes an LCD panel for displaying a picture image, and a driving part for applying a driving signal to the LCD panel. The LCD panel includes first and second glass substrates bonded to each other at a predetermined interval, and a liquid crystal layer injected between the first and second glass substrates. The first glass substrate (also called a TFT array substrate) includes a plurality of gate and data lines, a plurality of pixel electrodes, and a plurality of thin film transistors. The plurality of gate lines are formed on the first glass substrate at fixed intervals in one direction, and the plurality of data lines are formed at fixed intervals perpendicular to the plurality of gate lines. The plurality of pixel electrodes are respectively formed in a matrix configuration in pixel regions defined by the plurality of gate and data lines crossing each other. The plurality of thin film transistors are switched on/off according to signals of the gate lines for transmitting signals of the data lines to the respective pixel electrodes. The second glass substrate (also called a color filter substrate) includes a black matrix layer that excludes light from regions except the pixel regions of the first substrate, an R/G/B color filter layer displaying various colors, and a common electrode to obtain the picture image. In the case of an IPS mode LCD device, the common electrode is formed on the first glass substrate. A predetermined space is maintained between the first and second glass substrates by spacers, and the first and second substrates are bonded to each other by a sealant pattern having a liquid crystal injection inlet. The liquid crystal layer is formed using a liquid crystal injection method, in which the liquid crystal injection inlet is dipped into a container having a liquid crystal material while maintaining a vacuum state in the predetermined space between the first and second glass substrates. That is, the liquid crystal material is injected between the first and second substrates by an osmotic action. Then, the liquid crystal injection inlet is sealed with a sealant.
The LCD device is driven according to optical anisotropy and polarizability of liquid crystal. Liquid crystal molecules are aligned using directional characteristics because the liquid crystal molecules each have long and thin shapes. In this respect, an electric field is applied to the liquid crystal to control the alignment direction of the liquid crystal molecules. If the alignment direction of the liquid crystal molecules is controlled by the electric field, the light is polarized and changed by the optical anisotropy of the liquid crystal, thereby displaying the picture image. In this state, the liquid crystal is classified into positive (+) type liquid crystal having positive dielectric anisotropy and negative (−) type liquid crystal having negative dielectric anisotropy according to electrical characteristics of the liquid crystal. In the positive (+) type liquid crystal, a longitudinal axis of a positive (+) liquid crystal molecule is parallel to the electric field applied to the liquid crystal. In the negative (−) type liquid crystal, a longitudinal axis of a negative (−) liquid crystal molecule is perpendicular to the electric field applied to the liquid crystal.
FIG. 1 is an exploded perspective view illustrating parts of a general Twisted Nematic (TN) mode LCD device. As shown in FIG. 1, the general TN mode LCD device includes lower and upper substrates 1 and 2 bonded to each other at a predetermined interval, and a liquid crystal layer 3 formed by injecting a liquid crystal material between the lower and upper substrates 1 and 2.
The lower substrate 1 includes a plurality of gate lines 4, a plurality of data lines 5, a plurality of pixel electrodes 6, and a plurality of thin film transistors T. The plurality of gate lines 4 are formed on the lower substrate 1 in one direction at fixed intervals, and the plurality of data lines 5 are formed perpendicular to the plurality of gate lines 4 at fixed intervals, thereby defining a plurality of pixel regions P. Subsequently, the plurality of pixel electrodes 6 are respectively formed in the pixel regions P defined by the plurality of gate and data lines 4 and 5 crossing each other, and the plurality of thin film transistors T are respectively formed at crossing portions of the plurality of gate and data lines 4 and 5. Also, the upper substrate 2 includes a black matrix layer 7 that excludes light from regions except the pixel regions P, an R/G/B color filter layer 8 for displaying various colors, and a common electrode 9 for displaying a picture image. The thin film transistor T includes a gate electrode protruding from the gate line 4, a gate insulating layer (not shown) on an entire surface of the lower substrate 1, an active layer on the gate insulating layer above the gate electrode, a source electrode protruding from the data line 5, and a drain electrode opposite to the source electrode. Also, the pixel electrode 6 is formed of a transparent conductive metal material having the increased light transmittance, such as indium-tin-oxide (ITO).
In the aforementioned TN mode LCD device, liquid crystal molecules of the liquid crystal layer 3 positioned on the pixel electrode 6 are aligned according to a signal applied from the thin film transistor T, and light transmittance through the liquid crystal layer 3 is controlled by the alignment of the liquid crystal layer 3, thereby displaying the picture image. Also, the liquid crystal molecules are driven according to an electric field perpendicular to the lower and upper substrates, thereby obtaining increased light transmittance and high aperture ratio. The common electrode 9 of the upper substrate 2 serves as a ground, whereby it is possible to prevent liquid crystal cells from being damaged by static electricity. However, the TN mode LCD has disadvantageous characteristics such as a narrow viewing angle.
In order to solve this problem, an IPS mode LCD device has been proposed. FIG. 2 is a cross-sectional view illustrating a general IPS mode LCD device. As shown in FIG. 2, a pixel electrode 12 and a common electrode 13 are formed on a lower substrate 11. Then, an upper substrate 15 is bonded to the lower substrate 11 at a predetermined interval therebetween, and a liquid crystal layer 14 is formed between the lower and upper substrates 11 and 15. The liquid crystal layer 14 is driven according to an electric field parallel to the lower and upper substrates 11 and 15 between the pixel electrode 12 and the common electrode 13.
FIG. 3A and FIG. 3B illustrate the alignment direction of liquid crystal when a voltage is turned off/on in the IPS mode LCD device. FIG. 3A illustrates the IPS mode LCD device when the voltage is turned off. For example, when an electric field parallel to the lower and upper substrates is not applied to the common electrode 13 or the pixel electrode 12, there is no change in alignment of the liquid crystal layer 14. In more detail, the liquid crystal molecules are twisted at 45° with reference to the pixel electrode 12 and the common electrode 13. FIG. 3B illustrates the IPS mode LCD device when the voltage is turned on i.e., when an electric field parallel to the lower and upper substrates is applied to the common electrode 13 and the pixel electrode 12. Accordingly, the alignment direction of the liquid crystal layer 14 is changed. In more detail, the alignment of liquid crystal layer 14 is twisted more at 45° as compared to the alignment of liquid crystal layer when the voltage is turned off. In this state, the horizontal direction of the common and pixel electrodes 13 and 12 is identical to the twisted direction of liquid crystal molecules.
As mentioned above, the IPS mode LCD device has the common electrode 13 and the pixel electrode 12 on the same plane. Thus, it has advantageous characteristics such as a wide viewing angle. For example, along a front direction of the IPS mode LCD device, a viewer can have a viewing angle of 70° in all directions (i.e., lower, upper, left, and right directions). Furthermore, the IPS mode LCD device has simplified manufacturing process steps, and reduced color shift. However, the IPS mode LCD device has the problems of low light transmittance and low aperture ratio because the common electrode 13 and the pixel electrode 12 are formed on the same substrate. Also, in the case of the IPS mode LCD device, a rapid response time is required, and it is necessary to maintain a uniform cell gap due to a small misalignment margin.
FIG. 4A and FIG. 4B are perspective views illustrating the operation of the IPS mode LCD device when the voltage is turned on/off. As shown in FIG. 4A, when the electric field parallel to the lower and upper substrates is not applied to the pixel electrode 12 or the common electrode 13, the alignment direction 16 of the liquid crystal molecules is the same as an alignment direction of an initial alignment layer (not shown). As shown in FIG. 4B, when the electric field parallel to the lower and upper substrates is applied to the pixel electrode 12 and the common electrode 13, the alignment direction 16 of the liquid crystal molecules corresponds to a direction 17 of the applied electric field.
Hereinafter, a related art LCD device will be described with reference to the accompanying drawings. FIG. 5 is a plan view illustrating an IPS mode LCD device according to the related art, and FIG. 6 is a cross-sectional view taken along lines I-I′ and II-II′ of FIG. 5. FIG. 7 is a plane view illustrating another IPS mode LCD device according the related art, and FIG. 8 is a cross-sectional view taken along lines III-III′ and IV-IV′ of FIG. 7. FIG. 9 is a plane view illustrating another IPS mode LCD device according to the related art, and FIG. 10 is a cross-sectional view taken along lines V-V′ and VI-VI′ of FIG. 9.
As shown in FIG. 5 and FIG. 6, a gate line 61 including a gate electrode 61a is formed on a transparent lower substrate 60. Then, a common line 61b including a common electrode 61c and a first storage electrode 61d is formed in parallel to the gate line 61 within a pixel region. After that, a gate insulating layer 62 of SiNx or SiOx is formed on an entire surface of the lower substrate 60 including the gate line 61 and the common line 61b. Also, an island-shaped active layer 63 is formed on the gate insulating layer 62 above the gate electrode 61a. In order to define the pixel region, a data line 64 is formed on the gate insulating layer 62 perpendicular to the gate line 61. The data line 64 includes source/drain electrodes 64a/64b overlapped with both sides of the active layer 63. The plurality of common electrodes 61c are formed as one body with the common line 61b parallel to the data line 64 within the pixel region. Then, a pixel electrode 64d extending from the drain electrode 64b are formed between the common electrodes 61c, and a second storage electrode 64c extending from the pixel electrode 64c is formed on the common line 61b and the first storage electrode 61d. In the aforementioned structure, the drain electrode 64b and the pixel electrode 64d are formed on the same layer as the second storage electrode 64c in one body. After that, an upper substrate 50 is formed opposite to the lower substrate 60. The upper substrate 50 includes a black matrix layer 51 that excludes light from regions except the pixel regions of the lower substrate 60, and an R/G/B color filter layer 52 corresponding to the pixel regions of the lower substrate 60. The black matrix layer 51 is formed to cover the interval between the data line 64 and the adjacent common electrode 61c. Furthermore, the black matrix layer 51 is formed as a large dimension because of the bonding margin of the lower and upper substrates corresponding the data line 64, the gate line 61 and the thin film transistor TFT.
However, the IPS mode LCD device according to the related art has the following disadvantages. The opaque common line (electrode) and the pixel electrode are formed at predetermined portions of the pixel region, thereby lowering the aperture ratio. Also, the black matrix layer is formed to have a large dimension because of the bonding margin of the lower and upper substrates to prevent light leakage between the gate line and the common line, whereby the aperture ratio lowers.
In order to improve the aperture ratio, another IPS mode LCD device according to the related art will be described. As shown in FIG. 7 and FIG. 8, a gate line 81 including a gate electrode 81a is formed on a transparent lower substrate 80. Then, a common line 81b including a common electrode 81c and a first storage electrode 81d is formed in parallel to the gate line 81 within a pixel region. After that, a gate insulating layer 82 of SiNx or SiOx is formed on an entire surface of the lower substrate 80 including the gate line 81 and the common line 81b, and an island-shaped active layer 83 is formed on the gate insulating layer 82 above the gate electrode 81a. In order to define the pixel region, a data line 84 is formed on the gate insulating layer 82 perpendicular to the gate line 81. The data line 84 includes source/drain electrodes 84a/84b overlapping both sides of the active layer 83. At this time, a second storage electrode 84c is formed on the common line 81b and the first storage electrode 81d. The plurality of common electrodes 81c are formed as one body with the common line 61b parallel to the data line 64 within the pixel region. First and second contact holes 87a and 87b are formed in the drain electrode 84b and the second storage electrode 84c. An insulating interlayer 85 is formed on the entire surface of the substrate including the data line 84 in state of forming first and second contact holes 87a and 87b in the drain electrode 84b and the second storage electrode 84c. Also, a pixel electrode 86 is formed between the common electrodes 81c to be connected with the drain electrode 84b and the second storage electrode 84c through the first and second contact holes 87a and 87b. In the aforementioned LCD device, the pixel electrode 86 is formed of a transparent conductive layer. Also, the drain electrode 84b is formed on the same layer as the second storage electrode 84c, and on the different layer from the pixel electrode 86. Next, an upper substrate 70 is formed opposite to the lower substrate 80. The upper substrate 70 includes a black matrix layer 71 that excludes light from regions except the pixel regions of the lower substrate 80, and an R/G/B color filter layer 72 corresponding to the pixel regions of the lower substrate 80. The black matrix layer 71 is formed to cover the interval between the data line 84 and the adjacent common electrode 81c. Furthermore, the black matrix layer 71 is formed as a large dimension because of the bonding margin of the lower and upper substrates corresponding to the data line 84, the gate line 81 and the thin film transistor T.
The IPS mode LCD device explained in FIG. 7 and FIG. 8 has the following disadvantages. In the IPS mode LCD device of FIG. 7 and FIG. 8, the pixel electrode is formed of the transparent material, whereby it is possible to improve the aperture ratio as compared with that of the IPS mode LCD device explained in FIG. 5. However, because the common line (electrode) is formed at the predetermined portion of the pixel region, the aperture ratio lowers. Furthermore, the black matrix layer is formed as a large dimension because of the bonding margin of the lower and upper substrates to prevent light leakage between the gate line and the common line, whereby the aperture ratio is lowered.
In order to improve the aperture ratio, another IPS mode LCD device according to the related art will be described as follows. As shown in FIG. 9 and FIG. 10, a gate line 101 including a gate electrode 101a is formed on a transparent lower substrate 100, and a first common line 10b is formed in parallel to the gate line 101 within a pixel region. Then, a gate insulating layer 102 of SiNx or SiOx is formed on an entire surface of the lower substrate 100 including the gate line 101 and the first common line 101b, and an island-shaped active layer 103 is formed on the gate insulating layer 102 above the gate electrode 101a. In order to define the pixel region, a data line 104 is formed on the gate insulating layer 102 perpendicular to the gate line 101. The data line 104 includes source/drain electrodes 104a/104b overlapping both sides of the active layer 103. A storage electrode 104c is formed as one body with the drain electrode 104b and overlaps the first common line 101b. An insulating interlayer 105 is formed on the entire surface of the lower substrate 100 including the data line 104. The insulating interlayer 105 has a contact hole 106 on the drain electrode 104b and the storage electrode 104c. Also, a pixel electrode 107c is connected to the drain electrode 104b and the storage electrode 104c through the contact hole 106. The pixel electrode 107c is parallel to the data line 104 within the pixel region. Simultaneously, a second common line 107a is formed on the gate line 101, and a common electrode 107b is formed between the pixel electrode 107c and the data line 104 adjacent to the pixel region. The common electrode 107b is formed as one body with the second common line 107a. The pixel electrode 107c, the second common line 107a and the common electrode 107b are formed of a transparent conductive layer on the same layer. The first common line 10b and the second common line 107a are connected to each other in a non-display region, and the same common voltage is additionally applied to the first common line 10b and the second common line 107a. Then, an upper substrate 90 is formed opposite to the lower substrate 100, the upper substrate 90 including a black matrix layer 91 that excludes light from regions except the pixel regions P of the lower substrate 100, and an RIG/B color filter layer 92 corresponding to the pixel regions P. Although not shown, the lower and upper substrates are bonded to each other with a sealant in state of forming a liquid crystal injection inlet between the lower substrates.
In the IPS mode LCD device explained with reference to FIG. 9 and FIG. 10, the common electrode and the pixel electrode are formed of the transparent material, whereby it is possible to obtain the high aperture ratio. However, because the color filter layer is formed on the upper substrate, it may generate misalignment problems between the pixel region and the color filter layer when bonding the lower and upper substrates to each other. As glass substrates become large, the position difference is increased between the pixel region of the lower substrate and the color filter layer of the upper substrate. In order to overcome these problems, it is necessary to obtain a design that resolves the misalignment problem. In case of the design for solving the problem of the misalignment, the aperture ratio lowers after bonding the lower and upper substrates to each other.
Accordingly, a COT-structure (Color filter On TFT array) LCD device forming a color filter layer on a lower substrate is recently developed in order to overcome the problem of the position difference between the pixel region of the lower substrate and the color filter layer of the upper substrate. The COT-structure LCD device according to the related art will be briefly described. FIG. 11 is a cross-sectional view taken along line VI-VI′ of FIG. 9 and illustrates a related art IPS mode LCD device having a COT structure therein. That is, a gate line (‘101’ of FIG. 9) including a gate electrode (‘101a’ of FIG. 9) is formed on a lower substrate 100. Then, a gate insulating layer 102 is formed on an entire surface of the lower substrate 10 including the gate line, and an island-shaped active layer (‘103’ of FIG. 9) is formed on the gate insulating layer 102 above the gate electrode. In order to define a pixel region, a data line 104 is formed on the gate insulating layer 102 perpendicular to the gate line, the data line 104 including source/drain electrodes (‘104a’ and ‘104b ’ of FIG. 9) overlapping both sides of the active layer. Then, an insulating interlayer 105 is formed on the entire surface of the substrate including the data line 104, and R/G/B color filter layers are formed on the insulating interlayer 105 of the respective pixel regions. If the R/G/B color filter layers are overlapped above the data line 104, it decreases the planarization effect of an organic insulating layer formed on the color filter layer. Accordingly, it is necessary to obtain a sufficient margin ‘c’ in due consideration of accuracy when forming the color filter layer. For example, when forming the color filter layer, position accuracy is about ±3 μm, whereby it requires the minimum margin ‘c’ of 6 μm on the designing process, and it generates a maximum interval of 12 μm on the practical manufacturing process. That is, the color filter layer overlaps both sides of the data line 104, and the color filter layer is not formed above the center of the data line 104. After that, the organic insulating layer 109 is formed on the entire surface of the substrate to flatten the surface of the substrate, and a contact hole (‘106’ of FIG. 9) is formed in the drain electrode (‘104b’ of FIG. 9). Also, a pixel electrode 107c is formed in parallel to the data line 104 within the pixel region and connected to the drain electrode through the contact hole. Simultaneously, a second common line 107b is formed between the pixel electrode 107c and the data line 104 adjacent to the pixel region. When the second common line 107b is formed above the data line 104, the second common line 107b is wider than both sides of the data line 104 in the extent of ‘a’ and ‘b’, wherein ‘a’ is formed in the same width as ‘b’. The second common line 107b is formed at a width of approx. 4 μm.
However, the IPS mode LCD device having the COT structure has the following disadvantages. As shown in FIG. 11, the color filter layer is not formed above the predetermined portion of the data line to prevent the decrease of the planarization effect, thereby decreasing a contrast ratio by the reflection of the external light in the predetermined portion of the data line having no color filter layer. In order to solve this problem, a resin BM may be formed above the predetermined portion of the data line having no color filter layer. However, the resin BM is expensive, has low electrical characteristics due to its low resistivity, and generates the problem of impurity contamination on the particle source.